This invention relates to a multiprocessor and, more particularly, to a multiprocessor system having a shared memory.
FIG. 9 is a diagram showing the configuration of a mobile communications system. The system includes a stationary network 1 comprising local telephone switches 1a, 1b, a tandem switch 1c and a gateway switch id, etc., and a mobile network 2 comprising a mobile gateway switch 2a, a home location register (HLR) 2b, which manages subscriber class and location registration information for the purpose of providing service to mobile units, and a mobile switch 2c that refers to the home location register (HLR) 2b to decide base-station controllers (RNC) 3a, 3b, which carry out wireless control.
The base-station controllers (RNC) 3a, 3b are connected to the mobile switch 2c, which is a host device, and to a multimedia signal processor (MPE) 4, and have a function for executing processing in accordance with a command and a function for sending and receiving data to and from base stations 5a, 5b. Each of the base stations 5a, 5b communicates wirelessly with a number of user devices (mobile stations) 6a, 6b present in the cell that is under the control of the base station. A stationary telephone 7 is connected to the stationary network 1, and a PHS base station 9 is connected to the stationary network 1 via a PHS adapter 8.
Each of the base station controllers 3a, 3b is implemented by a multiprocessor. FIG. 10 illustrates the multiprocessor structure of each base station controller from which portions for sending and receiving signals to and from the outside have been omitted. Connected to a G bus 10 serving as a common bus are a bus arbiter (BCONT) 11 for performing bus allocation control, a plurality of processors (CPU #1 to CPU #n) 121 to 12n, and a common memory card (CM) 13. The processors CPU #1 to CPU #n are identically constructed and each has a microprocessing unit (MPU) 21 and an access controller (LSI) 22 for controlling access to the common memory card (CM) 13. The common memory card (CM) 13 has a common memory 23 comprising a RAM, and a common-memory controller (CM controller) 24. The common memory 23 has a data storage section GM equipped with a number of data storage areas A to N, and an exclusive control data storage section (semaphore register) semf for retaining whether respective ones of the storage areas A to N are presently in use or not as well as the names of processors presently in use. A storage area for which a busy flag has been set cannot be accessed by another processor.
The bus arbiter 11 and the processors CPU #1 to CPU #n are connected by respective ones of signal lines in the manner shown in FIG. 11. When the bus is not in use, each processor requests the privilege to use the bus by sending a bus-use request signal *BREQj from its signal line to the bus arbiter 11. If the right to use the bus is to be given to a prescribed processor, the bus arbiter 11 sends a bus-use enable signal *BGNTj to this processor. It is required that a processor output a bus busy signal *BB during a data transfer. Other buses refer to the bus busy signal *BB and cannot use the bus if it is in use.
In a case where a prescribed processor, e.g., processor CPU #n, is to acquire the bus-use privilege and access data storage area GM-A of data storage section GM, the processor sets a busy flag (exclusive control flag) in the corresponding storage area a of the corresponding semaphore register semf if the data storage area GM-A is not in use. The processor CPU #n thenceforth accesses the data storage area GM-A and reads out or writes data. If it becomes unnecessary to access the data storage area GM-A, then the processor clears the exclusive control flag that has been stored in the storage area a of the semaphore register semf. As a result, the other processors CPU #1 to CPU #n-1 are capable of accessing the data storage area GM-A.
With the conventional method of accessing the common memory card CM by multiprocessor processing according to the prior art, it is required that other processors CPU #1 to CPU #n-1 that desire to access the data storage area GM-A being used by the processor CPU #n read the content of the semaphore register semf whenever the bus-use privilege is obtained and check to determine whether the exclusive control flag corresponding to the data storage area GM-A has been set. If the exclusive control flag has been set, the processors similarly determine, upon elapse of 2 μs, whether the exclusive control flag has been set and subsequently issue the common memory card CM a read instruction, which is for reading the semaphore register semf, endlessly until the flag is cleared. As a consequence, not only does the number of times the bus is accessed (the number of times the bus is used) become very large, as shown in FIG. 12, but there is also a sharp increase in rate of CPU use owing to the increase in the number of times access processing (limitless retry) is executed. This means that the original performance of the apparatus cannot manifest itself fully.
FIGS. 13 to 17 are diagrams useful in describing control for accessing the common memory card CM according to the prior art. The number of processors is assumed to be two, namely CPU #0 and CPU #1, in order to simplify the description. The semaphore register (exclusive control data storage unit) semf manages the right to access the data storage areas A to N in the common memory and uses {circle around (1)} the number of the CPU that has acquired the access privilege and {circle around (2)} an acquisition flag (exclusive control flag) as management information. With regard to the address range of the common memory CM managed by the semaphore register semf, it is so arranged that semf-a, semf-b, . . . , semf-n manage data storage areas GM-A, GM-B, . . . , GM-N, respectively.
Processing is executed as described below in order to acquire the right to access a prescribed storage area. Reference should be had to FIG. 13.
{circle around (1)} The MPU 21 within CPU #0 generates a read access for the purpose of semaphore acquisition. The target at this time is semf-a, which is in the semaphore register semf of common memory 23.
{circle around (2)} The access controller (LSI chip) within CPU #0 receives the access request of step {circle around (1)}, sends the read access to the common bus 10 and waits for the common memory card CM to send back the result of acquisition of semf-a.
{circle around (3)} The CM controller 24 receives the read access sent on the common bus and reads out the data of semf-a pertaining to this access.
{circle around (4)} If the read-out data of semf-a is not in use, then the CM controller 24 adds on management information such that CPU #0, which is the source of the current access, will be rendered busy, and writes the result back to semf-a. As a consequence, semf-a attains a state indicating that CPU #0 is busy.
{circle around (5)} The CM controller 24 sends the management information, which was written back to semf-a, on the common bus as loop data. The loop data indicates that acquisition by CPU #0 has succeeded.
{circle around (6)} The access controller 22 of CPU #0 receives the data sent back on the common bus, relays it to the MPU 21 and completes semaphore acquisition processing. At this time the CPU #0 will have acquired the right to access data area GM-A.
If the right to access data area GM-A corresponding to semf-a is acquired by the above processing, then CPU #0 commences access, as shown in FIG. 14.
{circle around (1)} CPU #0 starts executing processing. If it becomes necessary to read data from or write data to data area GM-A of common memory 23 in the course of processing, then access to the data area GM-A is sent from MPU 21.
{circle around (2)} The access controller 22 receives the access of step {circle around (1)}, sends read access to the common bus 10 and waits for data read out of the data area GM-A of common memory card CM to be sent back. It should be noted that read access is described as an example.
{circle around (3)} The CM controller 24 receives the read access sent on the common bus.
{circle around (4)} The CM controller 24 reads data out of the data-area GM-A pertaining to this read access. In the case of write, the CM controller 24 receives the data that is on the bus and writes this data to the data area GM-A.
{circle around (5)} The CM controller 24 sends the read-out data to the common bus as loop data.
{circle around (6)} The access controller 22 of CPU #0 receives the data sent back on the common bus and relays it to the MPU 21.
Steps {circle around (1)} to {circle around (6)} are repeated thenceforth until the processing by CPU #0 ends. The data in data area GM-A is updated whenever a write access is generated.
If it becomes unnecessary for CPU #0 to access data area GM-A, terminate processing is executed as shown in FIG. 15.
{circle around (1)} If processing by CPU #0 ends, the MPU 21 sends release access to semf-a in order to relinquish the right to access the data area GM-A. That is, the MPU 21 accesses semf-a to write data 0.
{circle around (2)} This write access is received temporarily by the access controller 22, which then sends a terminate report to the MPU 21. At this time processing on the side of the MPU is completed but post-processing is executed by the access controller 22.
{circle around (3)} Upon receiving the write access, the access controller 22 sends write access directed to semf-a out on the common bus.
{circle around (4)} The CM controller 24 receives the access (write access and data) sent out on the common bus.
{circle around (5)} The CM controller 24 writes the receive write data (=0) to semf-a of the semaphore register semf to restore semf-a to the unused state. As a result, a state in which other CPUs can access the data area GM-N is attained.
By virtue of this series of processing steps, CPU #0 is capable of updating data area GM-A of the common memory card CM.
Processing illustrated in FIG. 16 is executed if a read access for semaphore acquisition is generated by CPU #1 in a state in which access to data area GM-A corresponding to semf-a has been acquired by CPU #0 through the operation shown in FIG. 13.
{circle around (1)} The MPU 21 within CPU #0 outputs a read access for the purpose of semaphore acquisition. The target at this time is semf-a, which is in a semaphore register in common memory 23.
{circle around (2)} If the access controller within CPU #1 receives the access request of step {circle around (1)}, then the access controller 22 sends the read access to the common bus 10 and waits for the common memory card CM to send back the result of acquisition of semf-a.
{circle around (3)} The CM controller 24 receives the read access sent on the common bus and reads out the data of semf-a pertaining to this access.
{circle around (4)} Next, the CM controller 24 determines whether the read data in semf-a is in use. Since the data is in use, semaphore acquisition by the CPU #1 that was the source of the access fails. It should be noted that since CPU #0 is busy, no particular write-back processing for management information is executed and semf-a is such that the busy state of CPU #0 remains as is.
{circle around (5)} The CM controller 24 sends information indicative of semf-a acquisition failure to CPU #1 on the common bus as loop data.
{circle around (6)} The access controller 22 of CPU #1 receives the data sent back on the common bus and relays it to the MPU 21.
At this time CPU #1 fails to acquire the right to access data area MG-A corresponding to semf-a and subsequently repeats retry access until semf-a (the right to access data area MG-A) can be acquired.
In a case where the right to access data area MG-A corresponding to semf-a has already been acquired by CPU #0 and CPU #0 is currently accessing data area GM-A, the following processing illustrated in FIG. 17 is executed when CPU #1 repeats retry access to acquire the right to access semf-a: Access processing by CPU #0 is the same as the processing of steps {circle around (1)} to {circle around (6)} in FIG. 14. If semaphore-acquisition retry access by CPU #1 occurs in between periods of processing by CPU #0 under these conditions, the processing of steps {circle around (7)} to {circle around (12)} (which correspond to steps {circle around (1)} to {circle around (6)} in FIG. 16) is executed. As a consequence, the common bus 10 is put under pressure.
As a result, access that is output from CPU #0 is delayed and so is processing for relinquishing semf-a that has been acquired by CPU #0. In addition, semaphore-acquisition retry access from CPU #1 occurs during this period as well, as a result of which processing by both CPU #0 and CPU #1 is delayed.
The specification of Japanese Patent Application Laid-Open No. 6-274415 discloses a multiprocessor system having a common memory. In this multiprocessor system, each processor is provided with a cache memory. When a processor accesses the common memory, the type of access (read or write) and either read-out data or write data are stored in the cache memory. When another device writes data to the common memory, the data in the cache memory is invalidated. By adopting this arrangement, consistency between the common memory and cache memory can be maintained without monitoring the state of the bus. Moreover, the common memory need not be accessed if a hit is achieved with regard to the data that has been stored in the cache memory.
In the conventional multiprocessor system illustrated in FIGS. 10 to 17, the number of bus accesses (the number of times the bus is used) becomes very large, access output from a processor during use is delayed and so is processing for relinquishing the semf-a that has been acquired. Furthermore, an increase in the number of times access-retry processing is executed invites a sudden increase in rate of CPU use and lowers throughput.
Though the multiprocessor system described in the specification of Japanese Patent Application Laid-Open No. 6-274415 is advantageous in terms of provision of the cache memory, it does not provide a solution when contention occurs in accessing a common memory.